This invention relates generally to the generation of graphics signals. More specifically, preferred embodiments of this invention relate to an apparatus, system, and method for the generation of two-dimensional computer graphics at a relatively low cost.
In conventional graphics generation systems, in order to enhance a Central Processing Unit (xe2x80x9cCPUxe2x80x9d) so as to achieve an improved graphics generation, a graphics processor is utilized. However, the conventional graphics processor comprises a separate logic device that, in turn, requires a separate set of circuitry.
More specifically, the conventional solution is to add a dedicated two-dimensional graphics processor to the system. The graphics processor is programmed by the system CPU and carries out the graphics processing independently. Also, the graphics processor is considered to be a xe2x80x9cperipheralxe2x80x9d device that adds an additional cost and/or more complexity to the system.
Yet another conventional solution involves adding single instruction-multiple-data instructions, e.g., by utilizing conventional MMX techniques to enhance the graphics generation performance. However, an MMX system has to load operands one word at a time and cannot automatically perform two-dimensional operations. Also, additional instructions are required to combine the operands for the desired operation before storing the result back into memory.
Conventional graphics processors require a number of additional functions and/or devices. These functions and/or devices may comprise at least one of, e.g., the addressing logic, the memory interface with additional arbitration, the read caches and write buffers, a command interface, and various kinds of micro-programmed control units.
With a conventional graphics processor, it is necessary to either duplicate some of the address translation logic, or to perform the translation in the software. Either the address translation logic, or the software translation, is required so that the application can work with the virtual addresses, while the hardware works with the physical addresses.
If the address translation logic solution is chosen, this additional logic hardware results in an additional cost. Alternatively, if the software translation solution is chosen, a relatively lower logic hardware cost results. But this software translation solution has at least two additional disadvantages. First, the address protection provided by the memory management unit is lost. This loss of memory management address protection thus increases the chances of system failures in this software translation solution. Second, a linear region of virtual addresses may not necessarily translate into a contiguous region in physical memory space, if a paged system is employed in this software translation solution. Therefore, the software not only has to translate the addresses, but must also break up any single two-dimensional graphics operations into multiple operations that operate separately on each page, thus resulting in additional overhead. This additional overhead reduces the graphics performance in the conventional graphics processor implementations.
Accordingly, there is an industry need for a device and method for the generation of computerized graphics at a relatively low cost.
Embodiments of the present invention are best understood by examining the detailed description and the appended claims with reference to the drawings. However, a brief summary of embodiments of the present invention follows.
Briefly described, an embodiment of the present invention comprises a device and a method that provides for the improvement of a computerized graphics generation system. A preferred embodiment comprises a two-dimensional graphics generation system that is implemented at a relatively low cost.
For example, in a preferred embodiment, the graphics coprocessor is comprised of adding a relatively minimal amount of logic so as to achieve a high performance two-dimensional graphics output from a computerized system. In this exemplary embodiment, the graphics coprocessor is attached to the side of a CPU. In other words, the graphics coprocessor is essentially an extension of the internal architecture of the CPU and, therefore, not considered to be a xe2x80x9cperipheralxe2x80x9d device. In alternate arrangements, the CPU may be located between the bus and the graphics coprocessor.
In a preferred arrangement, the CPU is attached to the system via a data cache and a write buffer. In this preferred arrangement, the data that is read from a system memory is also placed in the data cache so that a subsequent access to the same data will only require access the cache. Thus, the data that is written to the system memory is also written to a write buffer, so that any writes that occur may then be queued up and sent to the main memory at an appropriate time. Further, the display refresh controller also reads the data from the system memory and converts the data into a signal so that it may be sent to a display.
Specifically, in this preferred arrangement, an embodiment of the invention sits essentially xe2x80x9cbehindxe2x80x9d the data cache/write buffer in the same way that the CPU is oriented. Thus, the graphics coprocessor obtains essentially the same performance benefits that the CPU enjoys.
In another preferred embodiment, the graphics coprocessor may be implemented into a computer system where the CPU already provides for a mechanism to extend the internal architecture. One arrangement of this exemplary embodiment is to combine the graphics coprocessor with an ARM940-type device. Of course, alternate embodiments may be utilized with any CPU that may be so configured. Also, alternate embodiments may be utilized with any CPU where relatively simple internal modifications may be made, so as to allow these additional instructions to be routed to a coprocessor.
These additional instructions may be preferably provided by an exemplary arrangement that comprises an interface logic portion to interface with the CPU, a control register portion, a pixel First In First Out (xe2x80x9cFIFOxe2x80x9d) array, a pixel processing logic portion and a control logic portion.
The interface logic portion provides a interface mechanism for the CPU to route the additional or new instructions to the graphics coprocessor together with any associated data. This interface logic portion also provides a path for returning the data and for providing hand-shake signals to inform the CPU when an instruction is complete.
The control register portion is preferably configured by the application software. This control register portion performs a control of the coprocessor operation. The control register portion is preferably a subset of the conventional control registers that comprise at least a portion of a conventional graphics processor. Also, parameters such as pixel counts, bits per pixel, raster operation codes, and foreground and background colors, and the like, may comprise a portion of these control register portions.
The FIFO array portion is preferably a memory device that may be configured to be between one and four FIFO""s, inclusively, depending upon the number of operands involved in the preferred two-dimensional graphics operation. Specifically, the input pixel data is loaded into these FIFOs. Also, the pixel processing logic processes the pixel data for the desired two-dimensional graphics rendering effect. Then the control logic portion controls the operation of the coprocessor, preferably utilizing a state machine.
Other arrangements and modifications will be understood by examining the detailed description and the appended claims with reference to the drawings.